The inventive concept relates to a semiconductor memory device, and more particularly, to a semiconductor memory device supporting a read data bus inversion (RDBI) function and a method of testing the semiconductor memory device.
Semiconductor memory devices increase an operating frequency in order to increase an operating speed and increase the number of data input/output pins DQs in order to increase the number of data bits that are simultaneously input/output. For example, ultra-high speed semiconductor memory devices operating at a frequency of 500 MHz or higher and having 32 data input/output pins DQs have been popularized.
When a plurality of data are simultaneously output to 32 data input/output pins DQs, the output data generates a considerable amount of noise typically called simultaneous switching noise (SSN). If the SSN increases, the waveform of the output data is damaged, thereby degrading signal integrity. In order to reduce the SSN, semiconductor memory devices adopt a read data bus inversion (RDBI) function of inverting and outputting data when the data is changed above a threshold number.
The RDBI function reads data transmitted to data input/output pins DQs, if the number of data having a high level “H” is greater than the number of data having a low level “L”, outputs the data, and if the number of the data having the low level “L,” is lower than the number of data having the high level “H”, inverts and outputs the data. Semiconductor memory devices supporting the RDBI function must be tested in order to determine whether the RDBI function is normally performed.
In order to test the RDBI function, test equipment for testing a semiconductor memory device provides test patterns that expect data which are input to data input/output pins DQs to be output from the data input/output pins DQs in an inverted mode or a non-inverted mode. The inverted or non-inverted mode may be determined by using a data mask pin DM that sends an inverted flag signal. It takes much time and effort to provide the test patterns.
In order to test the RDBI function in the inverted mode, for example, if the test equipment provides an 8-bit input test pattern “00000111” to a semiconductor memory device having 8 data input/output pins DQs, it is expected that bits “111111000” are output from the data the data input/output pins DQs of the semiconductor memory device and an inverted flag signal having a logic level “1” is output from the data mask pin DM. However, if bits “00000111” are output from the data input/output pins DQs of the semiconductor memory device and an inverted flag signal having a logic level “0” is output from the data mask pin DM, although the RDBI function of the semiconductor memory device passes the test, the test equipment determines that the RDBI function of the semiconductor memory device fails the test. On the contrary, in order to test the RDBI function the non-inverted mode, if the test equipment provides an 8-bit input test pattern “111111000” to the semiconductor memory device, it is expected that bits “11111000” are output from the data input/output pins DQs and an inverted flag signal having a logic level “0” is output from the data mask pin DM. However, if bits “00000111” are output from the data input/output pins DQs and an inverted flag signal having a logic level “1” is output from the data mask pin DM, although the RDBI function of the semiconductor memory device passes the test, the test equipment determines that the RDBI function fails the test, which causes an over-kill problem.
In more detail, if an RDBI logic circuit of the semiconductor memory device is implemented as an analog circuit and an RDBI condition is not satisfied due to a timing margin or a process change, an inverted flag signal may be sent and read data may be inverted. In this case, although a RDBI function passes a test by comparing data in real time, it is regarded as failing the test.
Accordingly, there is a demand for a method of determining an RDBI function only by testing an existing input test pattern, without calculating input test patterns and output test patterns corresponding to the input test patterns and generating a test screen pattern.